1. Field of the Disclosure
The disclosure generally relates to a method of forming patterns of a semiconductor device and, more particularly, to a method of forming micro patterns of a semiconductor device.
2. Brief Description of Related Technology
A number of elements, such as gates or isolation layers, are formed in a semiconductor substrate. Metal wiring lines are also formed in order to electrically connect the gates. The metal wiring lines and a junction (for example, the source or drain of a transistor) of the semiconductor substrate are electrically connected by a contact plug.
The gates, the metal wiring lines, etc. are generally formed by a pattern formation process. That is, a target etch layer (for example, a gate stack layer, a conductive layer or an insulating layer) whose pattern will be formed on the semiconductor substrate is formed. An etch mask pattern is formed on the target etch layer. The target etch layer is patterned by an etch process employing an etch mask pattern. A micro pattern is formed using the pattern formation process. Heretofore, that process was considered an indispensable process of forming semiconductor devices with an ultra-small size and high performance. However, the size of a pattern that can be formed is limited due to the limitations of equipment used in the pattern formation process, and the difficulties in overcoming those limitations.